In this situation, if the /SS input is pulled low while the 68HC11 is the master, the processor detects a "mode fault" (by setting a bit in the SPI status register) meaning that there is more than one master device on the SPI bus. The /SS pin can be configured as either an input or an output. You can use the QED Board’s RS485 link to create such a multi-drop serial network. For RS485 operation: Install the jumper shunt across the two pins closest to the J3 silk screen. With this boards, a CBL03 lines with RJ11 connectors can branch out to support an RS485 line consisting of three discrete wires. If the CPHA bit is 1, the /SS line may be tied low between successive transfers. To interface devices that support synchronized serial interfaces, but are not configurable like the 68HC11, determine the device’s requirements for clock phase and polarity and configure the 68HC11’s CPHA and CPOL accordingly. This section also defines the logic states 1 (off) and 0 (on), by the polarity between A and B terminals.

The next section describes the registers that configure and control the QScreen Controller’s SPI. When the keyword name is received by the Silence() routine running in the slave, the slave QScreen Controller executes RS485Transmit() to send an acknowledgment to the master (which should now be listening to the serial bus to accept the acknowledgment). Setting the MSTR bit initializes the QScreen as a master, and clearing the MSTR bit initializes it as a slave. If the 68HC11 is initialized as a master by setting the MSTR bit, then bit 5 of the Port D data direction register (PORTD.DIRECTION) determines whether /SS is an input or an output. Setting the MSTR bit initializes the 68HC11 as a master, and clearing the MSTR bit initializes it as a slave. Initializing the 68HC11 as a slave (by clearing the MSTR bit in the SPCR control register as explained below) automatically configures the /SS pin as an input. A mode fault occurs when the SPI senses that a multimaster conflict (MC68HC11F1 Technical Data Manual, p.10-5) exists on the network as explained above in connection with the /SS input. A mode fault occurs when the SPI senses that a multimaster conflict (MC68HC11F1 Technical Data Manual, p.8-7) exists on the network as explained above in connection with the /SS input.

RS-485 standard conformant drivers provide a differential output of a minimum 1.5 V across a 54-Ω load, whereas standard conformant receivers detect a differential input down to 200 mV. RS-485 does not define a communication protocol; merely an electrical interface. In theatre and performance venues, RS-485 networks are used to control lighting and other systems using the DMX512 protocol. Set the PC to N81 for the Custom ASCII protocol, or to N82 or E81 for the Modbus RTU protocol. The 68HC11 allows the details of the synchronous communications protocol to be customized for compatibility with a variety of peripherals. When the 68HC11 controls the network, it is referred to as a "master"; otherwise, it is a "slave". To properly operate the network each slave computer executes RS232Silent at startup; thus all of the slave transmitters remain silent individually addressed by the master. The software routines, RS232Transmit() and RS232Silent() control the dual RS232 transmitters on the board. When a slave is addressed, it executes RS232Transmit() at which point full duplex (two-way) communications commences between the master and the selected slave. This allows standard point-to-point full duplex communications, as well as a multi-drop configuration with one master (a single QVGA Controller or a desktop computer) and multiple QVGA Controller slaves.

Pre-coded device drivers configure the SPI for a standard data format, and routines defined in this chapter make it easy to customize a data format and baud rate for your application. 1 running at the prior established baud rate (typically 9600 baud). If you do this now, remember to move the QVGA Controller’s serial connector back to Serial Port 1, and to change the terminal’s baud rate back to 9600 baud using the "Communications" item under the terminal’s "Settings" menu. The new baud rate takes effect upon the next reset or restart. At the start of a transmitted character, the service routine takes about 65 µs. In most cases the times are less than 25 µs which does not pose a problem. We are customer driven. Many of our products were developed and improved due to suggestions and feedback from our word-wide customer base. The QED-Forth kernel includes pre-coded drivers that configure the SPI for maximum speed data transfer using a format that is compatible with the on-board D/A and 12 bit A/D. The QVGA Controller’s on-board 12 bit A/D and 8 bit D/A converters communicate with the processor via the SPI.

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